Integrated circuit memory devices are often organized into rows and columns of memory cells, with the rows and columns separately selected based on the value of the portions of the memory address which represent row and column addresses. In such devices, the term "word lines" generally refers to a set of conductors of which one, when active, selects the addressed row of memory cells; the term "bit lines" generally refers to a set of conductors which communicate data between memory cells in the addressed row and a sense amplifier. The sense amplifier is a circuit which senses the data state of the data on an associated bit line, and which generally amplifies the sensed data state for communication to output stages of the circuit.
Due to the drive capability of static memory cells, where the memory cell consists of a latch, multiple columns in many static random access memories (SRAMs) share a single sense amplifier. For purposes of sensing resolution, however, generally the shorter the bit lines associated with a single sense amplifier, the smaller the differential voltage which is detectable by a sense amplifier. It is therefore preferable for purposes of sensing to provide a single sense amplifier for each column in the memory cell array.
However, the provision of the many sense amplifiers required to have one sense amplifier per column increases the load that a particular sense amplifier is required to drive. In a 256 kbit SRAM organized into 256 rows by 1024 columns, for example, 1024 sense amplifiers must be provided for a one-to-one correspondence between sense amplifiers and columns. The sense amplifier which is associated with the selected column must thus be capable of driving a data line which is connectable to the 1023 other sense amplifiers. The capacitive load of such a long data line, especially including the parasitic load provided by isolation transistors decoupling the unselected sense amplifiers from the data line, either requires the provision of large drive transistors in each sense amplifier, or results in reduction in read access time performance. It should be noted that in the architecture where a single sense amplifier is provided for each column, the space required for a sense amplifier in one dimension (i.e., the sense amplifier pitch) can be no greater than the space required for providing a column of memory cells (i.e., the column pitch), without significantly expanding the size of the integrated circuit required for incorporating the SRAM device; such a pitch constraint will, of course, limit the size of the drive transistors which can be provided within the sense amplifier.
It is therefore an object of this invention to provide a sensing and decoding scheme for a static RAM device which allows for a reduced data line load for sense amplifiers.
It is a further object of this invention to provide such a scheme for an SRAM having a single sense amplifier for each column of memory cells.
It is a further object of this invention to provide such a scheme realized in BiCMOS technology.
Other objects and advantages of the instant invention will become apparent to one of ordinary skill in the art having reference to the following specification, in conjunction with the accompanying drawings.